This step is also demoed with this video :

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Step 5a : Defining Sample Time in the architecture

Previous step 5 explained how to design the Simulink model of an architecture, for example with architecture archi_training_vU12d1 :

Step 0a explained how to execute a module, with or without a port trigger :

By specifying the St parameter of a module in an assembly (see step 0a), you can typically have this kind of layout :

It is also possible to specifiy nothing or -1 :

Assume that all modules of room 2 are sampled in this way, then we have this layout :

These modules are exectued according to the upper levels parameters.

In this case, it might be useful to specify a sample in the architecture, at a floor or a room level.

For example, if you wish that all modules of room 2 are exectued at 10ms :

you can specifiy in the architecture that this room executes its modules at 10ms, using the Sample Time Simulink parameter of the SubSystem.

For example, suppose that in the architecture archi_training_vU12d1, room mon_ has to execute its modules at 10ms :

then, in the architecture, you can simply define Sample Time of this subsystem to 10ms :

Then, you have the expected situation :

As a result, such a situation will not be allowed because sample time layout is not consistent :

You can also specify a sample time at any level in an architecture, as long as sample time layout is consistent.

At a floor level for example :

or at the top level of the architecture :

Of course, sample time layout must be consistent, this layout for example is not consistent :

As an example in this step, in archi_training_vU12d1 :

• • floor MEASUREMENTS including rooms ana_ and can_ is sampled at 10ms

  • room mon_ is sampled at 10ms

Remark : though this way to specify execution time is possible, this method should be used only for specific context..

Indeed, if rooms are sampled without constitency, Simulink model of an assembly may not be runnable.

As an example, abl_training_vU1d4 is not consistent because :

• • room mon_ is sampled at 10ms

  • but module FB_LatAcc_v006d000 is sampled at 20ms

As a result, as FB_LatAcc_v006d000 sampled at 20ms feeds mon_system_v000d000 sampled at 10ms, communication between these signals must be handled with a Rate Transition block.

If you auto assemble abl_training_vU1d4, this Simulink error appears :

A rate transition block should be inserted before room mon_ but MTX only intervenes inside the rooms.

For this reason, it is rather recommended to use St parameter with a trigger port, or Sample Time property of the module :

-> it makes an architecture independant of the execution.

Step 5 and 5a explained how to design an architecture.

As a result, some conditions are necessary to make an architecture valid for an assembly.

This is explained next step 5b.

Published with MATLAB® R2013a