This step is also demoed with this video :

(ongoing...)

Step 7e : insertRT, rtIntegrity & rtDetermnisitic

Remark : this option has also been introduced at step 2a.

In the options, default value for insertRT is 1 (but has been preset to 0 for this particular step) :

When set to 1 and during an auto assembly, a Rate Transition is automatically inserted for each signal entering a module.

Let's consider the assembly abl_training_vU10 attached to the empty architecture archi_empty_vU0.

This assembly contains following modules :

• • ana_loop6_vU0 running at 0.010s

  • ana_loop7_vU0 running at 0.020s

In this context, option insertRT has been set to 0 :

Then, ask a auto assemble by pressing the AUTO button. Result is :

As we can see, a signal calculated at 10ms is feeding a module running at 20ms.

This has to be handled : for explanations by MathWorks about what to handle, see Handle Rate Transitions.

One way to handle it is to check on 'Automatically handle rate transition for data transfer' (see MathWorks documentation for better understanding).

The other way is to insert the rate transition block from Simulink when necessary (see MathWorks documentation for better understanding) :

Typically, signal ana_loop6 needs a rate transition block. If not, Ctrl+D (update diagram) leads to an error :

Option insertRT is useful to automatically insert rate transition block. Then, if you set this options back to 1 :

Then, by auto assembling again with this new option, result is :

Ctrl+D (update diagram) does not lead to any error.

Remark 1 : the RT blocks are parametrised according to both options rtIntegrity and rtDeterministic (see MathWorks documentation) :

Remark 2 : RT block manages signals only when necessary, when it's not necessary, RT block is visible but act as if it was not there (see MathWorks documentation)

Published with MATLAB® R2013a